Liquid crystal displays (LCD) are used today in an ever-increasing number of products such as cellular telephones, portable computers, etc. The displays, which can be in black and white, or in a grey or color scale, are usually made up of a matrix of electrodes in rows and columns. When driven by an appropriate voltage signal, a change in the optic behavior occurs at the crossing points of the rows and columns (“pixels”).
The image that is visualized on the display is obtained through different possible methods for driving the rows and the columns.
One method that is often used for driving an LCD is known as Improved Alt & Pleshko (IA&P) and requires a single row electrode to be excited for an elementary period of time by a single selection pulse and the simultaneous excitation of the column electrodes. Voltage values are then applied to the column electrodes suitable for causing all the pixels that belong to that single row to be turned on or turned off. For a successive period of elementary time there is an excitation of another row electrode and so on until the scanning of the last row electrode is completed; therefore if the row electrodes are a number N and T is the period of elementary time, the time needed for scanning all the rows will be given by NT which is also called a “frame”.
The optic transmission characteristics of the liquid crystal vary with the amplitude of the voltage applied to the relative pixel, but the application of direct voltage is damaging to the liquid crystal as it permanently changes and degrades the physical properties of the material. For this reason, the voltage signals used to drive the single pixels of an LCD are alternating voltage in relation to a common value of direct voltage that is not necessarily ground potential. In this manner, the driving of a pixel of the display comes about through two waveforms of equal amplitude but with opposite polarity in relation to a common voltage, that follow each other periodically. Therefore the driving voltage applied to a given pixel during its period T within a frame is applied with opposite polarity during the respective period T of the successive frame.
Nevertheless, all these voltage transitions involve significant power that has to be managed by the drive circuits. Therefore, one of the primary purposes in planning the LCD row and column driving devices is to reduce the power consumption to minimize both the power delivered by the power supplies of said devices, and the power dissipated by them.
One part of a driving device of LCD rows and columns, more precisely the Philips PCF8548 device, is shown in FIG. 1.
The LOW_FRAME signal is a logic signal that equals zero in the even frames, and equals one in the uneven frames. WHITE_PIX is a logic signal that equals zero when the pixel is on, and equals one when the pixel is off. Starting from these two signals are generated, through a circuit 1, the control signals that drive two PMOS transistors T9, T10 and two NMOS transistors T7, T8.
In particular, the gate terminals of transistors T8, T9 and T10 are driven through 3 identical circuit cells C1, shown in FIG. 2. Said cells are level-shifters that is, buffers that convert the logic signal levels from a low voltage to a high voltage, in particular, from the supply voltage VDD to a driving voltage VLCD generated by a device (not shown in FIG. 2) comprising a booster regulator through the connection of a certain number of stages of a charge pump.
Each cell C1 comprises two NMOS transistors M22 and M23 driven by signals A and NA, the output signal of the logic circuitry 1 and the negated signal A. The source terminals of transistors M22 and M23 are coupled to the voltage VSS and the drain terminals are respectively coupled to the drain terminals of two PMOS transistors M20 and M21 on the source terminal of which the voltage VLCD is present; in addition the drain terminals of transistors M22 and M23 are coupled to the gate terminals of transistors M21 and M20. The outputs Q drive the gate of transistors T10, T9 and T8.
The gate terminal of transistor T7 is driven directly by a logic low voltage signal.
The source terminal of the transistor T9 is connected to a voltage reference VA, while the drain terminal is coupled to the drain terminal of transistor T10, whose source terminal is coupled to the voltage VLCD. The source terminal of transistor T8 is coupled to a voltage reference VB, while the drain terminal is coupled to the drain terminal of transistor T7, whose source terminal is coupled to the voltage VSS. The drain terminals of the pairs of transistor T7-T8 and T9-T10 are in common and supply the output signal OUT.
The voltages VA and VB are different levels of intermediate voltages between the voltages VLCD and VSS that are generated inside the drive device of an LCD. The relation between these levels and VLCD is chosen on the basis of the dimension of the matrix of the display according to the criteria that is shown and described below.
In particular, according to the technique of Improved Alt & Pleshko, to drive the liquid crystal display adequately, four different voltage levels intermediate between VLCD and VSS are generated inside the device. The relation between these and VLCD is set on the basis of the number of rows m of the display according to the relations:VLCD,[(n+3)/(n+4)]*VLCD,[(n+2)/(n+4)]*VLCD, [2/(n+4)]*VLCD, [1/(n+4)]*VLCD,VSS)with n given by √m−3.
If, for example, m=81=>n=6 in the case of a display with 81 rows the voltage levels will be:VLCD (9/10)*VLCD (8/10)*VLCD (2/10)*VLCD (1/10)*VLCD VSS.
With reference to the drive circuit of FIG. 1, in the case of a drive of columns, the voltage references VA and VB are equal respectively to (8/10)*VLCD and (2/10)*VLCD. The drive is provided, for example, in the following manner: in a frame transistors T9 and T10 are turned on alternately, while transistors T7 and T8 are off; in this case the output signal OUT, suitable for driving a column, varies between VLCD and VA according to whether the corresponding pixel on the matrix of rows and columns given at the crossing point of the column and the row is on or not. In the successive frame transistors T7 and T8 are turned on alternately while transistors T9 and T10 are off and therefore the output signal varies between VSS and VB according to whether the pixel at the crossing point of the corresponding column and row is on or not. The waveforms of the output signal OUT in the case of driving two columns COL0 and COL1 for a frame n and for the successive frame n+1 are shown in FIG. 3. FIG. 4 shows the image as it appears on the display.
What is desired is a system for driving columns of a liquid crystal display that has lower current consumption in comparison to known prior art devices.